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Kxyxl_vxly's avatar
Kxyxl_vxly
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2 years ago

FPGA VERILOG

I am a final year student in mechatronics engineering . My final year project is to build a electronics voting system using DE10 Standard terasIC FPGA board in Quartus Verilog . The components that I...
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_AK6DN_'s avatar
_AK6DN_
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2 years ago

Go here:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1081#contents

And look at the documentation that TerASIC provides for that board.

In particular, look at the RESOURCES tab, and at the DE10-Standard SystemBuilder tool you can download.

It is a standalone windows program that can help you configure the I/O definition for the board resources/pinout
that you can then edit/alter as necessary for your project definition.

It will build a .qpf, .qsf, .sdc, and .v template files for you to start with.

You also might look at some of the examples provided on the DE10-Standard CD-ROM image that is provided.
It is very useful, if you don't already have that software and files you should.

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