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Honored Contributor[FPGA-to-SDRAM Avalon-MM Bridge] -> beginbursttransfer is missing...
Hi All, I'm working with the ArriaV device and going to use the FPGA-to-SDRAM Avalon-MM Bridge. Does the FPGA-to-SDRAM Avalon-MM Bridge support the burst transactions? After enablin...
Altera_ForumHonored Contributor
Honored ContributorWhat's the maximum memory space in SDRAM/DDR Memory could be occupied through the FPGA-to-SDRAM Avalon-MM Bridge?
Here are my calculations: FPGA-to-SDRAM Bridge has 27 address lines and 256 data lines. So, 2^27*256=2^27*32B=2^32B=4gb -> 4gb of SDRAM/DDR Memory might be occupied through the FPGA-to-SDRAM Bridge. Is that correct? What's the mapping? Should the 0x0000_0000 on the address lines of the FPGA-to-SDRAM Bridge indicate that the data will be also written to the address 0x0000_0000 in the SDRAM/DDR Memory? Thank you!
