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Altera_Forum
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10 years ago

FPGA-to-HPS bridge, too slow?

Hi, my co-worker is using the Cyclone V with the embedded ARM cores. I often stop by his cube and ask him his opinion of the SoC. His biggest complaint is the FPGA-to-HPS bridge which he says is a bi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Do You use altera macros for read/write to this virtual adresses? (alt_read_word, alt_write_word) This macros have casts to volatile pointers which tells compiler that memory caching should be skipped. This is not the same as just dereferencing standard pointers.

My memory map call looks like this, might be flags are different:

void * vbase = mmap(NULL,map_size, (PROT_READ | PROT_WRITE), (MAP_SHARED),mem_fd,(unsigned int)adress & ~(unsigned int)map_mask);