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Altera_Forum's avatar
Altera_Forum
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10 years ago

FPGA-to-HPS bridge, too slow?

Hi, my co-worker is using the Cyclone V with the embedded ARM cores. I often stop by his cube and ask him his opinion of the SoC. His biggest complaint is the FPGA-to-HPS bridge which he says is a bi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

OK, I also use Linux. I've not measured latency yet. My test runs for 10 seconds and I get very reproducable bandwidth for each run. How do You write to the bridge? Is it MM Interface and You do a mmap in Linux? Then read/write to virtual adress? Do You use interrupts?