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Altera_Forum
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16 years ago

FPGA PS config issue - FPGA not reporting invalid config bitstream

I have a quick question about passive serial configuration. I am using a MAX II CPLD to program an FPGA uisng an RBF file that is stored in flash. The issue I am having is as follows - before t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'm also using a modified MAX II PFL in a design, but I didn't yet experience the said behaviour, most likely because I didn't try with an erased flash. Your explanation sounds plausible to me, the FPGA seems to wait endlessly for a start of the config bitstream.

As the FPGA apparently doesn't have a timeout, it would be easy to add it in to the PFL design.