Hi, I need to do 18x7 multiplication and my FPGA doesnt have the built in DSP blocks, so I am using behavioral code in the source code to do the multiplication. It is taking around 190 LUT to do this multiplication Example: q_srrc_sum <= $signed(7'd63) * q_srrc; where q_srrc is an 18 bit vector I need to do 16 of these and it takes lot of the area. Is there a better way to optimize this , so that the resource utilization is less. Thank You

190 LUT seems a lot for multiplying by the constant 63 (0x3f if I read it right). That multiply should be one subtraction. If your multiplies are all by constants, you might be able to optimise them. I'm also surprised the multiply takes many more than 18x7 (126) LUT - since it can be made of that many full adders (3 input bits) with a delay of 18+7 (23 or so) logic steps. Reducing the resource either means using multi cycle multipliers, or muxing the values into a single multiplier.

--- Quote Start --- 190 LUT seems a lot for multiplying by the constant 63 (0x3f if I read it right). That multiply should be one subtraction. If your multiplies are all by constants, you might be able to optimise them. I'm also surprised the multiply takes many more than 18x7 (126) LUT - since it can be made of that many full adders (3 input bits) with a delay of 18+7 (23 or so) logic steps. Reducing the resource either means using multi cycle multipliers, or muxing the values into a single multiplier. --- Quote End --- if I want multiply any number by 64 then I just add 6 leading zeros. if I want multiply by 63 instead of 64 I will try see if the minor error can be tolerated. If not I will sunbtract: y * 63 = y*(64-1) = y*64 -y

Hi, Thank you for your response, can you please elaborate on this, I didnt follow what you meant by: if I want multiply any number by 64 then I just add 6 leading zeros. The synthesis tools are smart enough whether I use a Multiplier (*) in my source code or a shift operator correct and use the same resources??? Thank You.

Unfortunately I cannot add latency( 1-2 clock latency is fine nothing more than that). Is there any other option? Thank you for your response.

--- Quote Start --- Unfortunately I cannot add latency( 1-2 clock latency is fine nothing more than that). Is there any other option? Thank you for your response. --- Quote End --- If you just want to multiply any number (binary format) with any power of 2 constant e.g. 2^6(64) then all you need is insert 6 leading zeros e.g. 1 = '1', 2 = "10", 4 = "100" and so on. It does not need multiplier and I wouldn't wait for a tool to do that. If your constant is close to 2^n then you can subtract or add as appropriate e.g. 112 * 65 = 112*64 + 112 so add 6 leading zeros then add one more sample of input. regarding latency issue: you can insert leading zeros without any latency. for add/subtract you may need one clock or so depending on your design. For suitable bitwidths you may also think of precomputed Look-up-table.

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Altera_Forum

Honored Contributor

13 years ago

FPGA Multiplication Resource Utilization

Hi,

I need to do 18x7 multiplication and my FPGA doesnt have the built in DSP blocks, so I am using behavioral code in the source code to do the multiplication. It is taking around 190 LUT to do this multiplication

Example: q_srrc_sum <= $signed(7'd63) * q_srrc; where q_srrc is an 18 bit vector

I need to do 16 of these and it takes lot of the area. Is there a better way to optimize this , so that the resource utilization is less.

Thank You

11 Replies

Altera_Forum
Honored Contributor
13 years ago
Agreed. For multiplying by a fixed number, shifts, adds and subtracts are the way to go. I once wrote a program that would give you the optimal combination in pseudo code. I'll see if I can dig it up somewhere. It basically found two shift values that were above and below the multiplier and then recursively deduced the least expensive path.

-Mux

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FPGA Multiplication Resource Utilization

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