FPGA Multiplication Resource Utilization

Since an n-bit by m-bit multiply is basically n m-bit wide conditional adds (or m n-bit wide ones) somewhere you have to perform those operations. You can arrange to feed the 'carry' bits from one addition into the next, reducing the latency (the carry bits are the limiting factor) from 'n * m' to 'n + m' full addres cells.

If you have to do all your multiplies in the same clock, then you need separate logic for each.

If you can arrange to do them in different clocks than you can use mux to feed in the required values into a single (or smaller numer of) multiplier block.

You can also feed the bits of the operands into a smaller multiplier and add together the results (like doing a long multiply by hand). That is probably easiest if you just split one of the inputs into 2 equal pieces.