FPGA LCD Problem and Always Construct Problem

AIDCheng,

Not sure what exact your problem is but first thing first. Without reset sig, your output will come up in an undefined state (could be 1 or could be 0), it won't always be 0. (I'm sure if you look at warning in synthesis report, it'll warn you of undefined states.) Also, countOut is defined as 6-bit but only the first 5 bits are driven when done != 1 AND veri == 1, and countOut[5] will always remain undefined. Fixed these first and see what happen.

In addition, for best coding practice, always use non-block assignment (<=) in sequential construct (i.e., always statement). Take a look at blocking vs. non-blocking assignment. But basically, adopt doing this way:

assign output = sig1 & sig2; //Using = here.

always @(posedge clk or negedge reset_n)

begin

if(!reset_n)

output <= 1'b0; //reset to benign value

else if(sig1 & sig2)

output <= 1'b1; //Using <= here.

end

always@(negedge clk or negedge RESET_N)

begin

if (!RESET_N)

begin

Solvout <= 1'b0;

countOut <= 6'b000000;

end

else if ( (done != 1'b1) & (veri == 1'b1))

begin

//Put your logic here

end

end

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I am using the TerasIC DE2-115 with Cyclone IV with Quartus II 10.0 Web Edition and I have two problems:

problem a: lcd display

My first problem occurs in the LCD display. I am currently using a slightly modified version of: (remove parenthesis and spaces from (http: ))

(http: )//johnloomis.org/digitallab/lcdlab/lcdlab1/lcdlab1.html

where I created several additional input wires containing data to be displayed. However, when run on the FPGA, the LCD Display only displays the first set of data, and does not change/refresh when new data is inputted.

problem b: always construct

I have this weird problem when running a module (shown below). Basically, I have an oracle, in which this module sets an LED to high when it detects that there is a solution to the oracle. I also have another signal (register) which increments for every solution, and displays that number on LEDs.

module SolTest(clk, done, veri, Solvout, countOut);
  input clk, veri, done;
  output reg Solvout;
  output reg  countOut;
 
  always@(negedge clk)
  begin
    if((done!==1)&&(veri==1))
    begin
      Solvout = 1;  //1
      countOut = countOut + 5'b00001; //2
      //countOut = 5'b00001;  //3
    end
  end
 
endmodule

Note: I'm pretty sure that quartus sets an unknown value to 0. It did that for another module that I have. Does anyone know if this is true?

A top module connects the outputs to LEDS.

I'll list the problems I have here:

• module as it is shown (line 1 and 2 un-comment, 3 comment): all LEDs are off (meaning countOut = 5'b00000 and Solvout = 1'b0)

• module with 2 commented out, 3 un-commented (1 unchanged): LED for Solvout is off, LEDs for countOut makes binary 1 (5'b00001)

• module with 2 and 3 commented out (1 unchanged): LED for Solvout is on

To me, this defies logic. Does anyone know the problems?

I can give full code (for full oracle) at one's request.

[EDIT] As I am on a deadline, I would like to have a response soon...

Thanks~

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