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Yes I use PLL locked outputs as reset sources, but the reset code already compensates for possible locked signal toggling during resynchronization period after PLL reset is
deasserted. The design is fully constrained, there are no violations reported.
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Great, that eliminates transient timing related issues.
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the system wakes up, reads firmware header in EPCS, validates checksum, starts copying to RAM and than bum
it freezes - reset is not asserted.
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What is doing the copy from RAM? The bootloader?
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I didn't observe any freezes before execution of bootloader code and none after it - in fact it actually doesn't matter what code I run just after reset
it will likely freeze, could be a simple filling of RAM with zeroes.
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Ok, so once your code has jumped into main() and you fill RAM with zeros, you get a lock-up?
If you've got to the point that your processor is running, try using the NIOS debugger.
Cheers,
Dave
Honored Contributor
