FPGA instability after reset

Thanks for the SignalTap tip, but I am not sure what to look for - the system wakes up, reads firmware header in EPCS, validates checksum, starts copying to RAM and than bum

it freezes - reset is not asserted. I didn't observe any freezes before execution of bootloader code and none after it - in fact it actually doesn't matter what code I run just after reset

it will likely freeze, could be a simple filling of RAM with zeroes. I've tried many variations, but long pause after PLL reset fixes it - or I should better say masks the actual problem.

I also build a minimal test system - just nios2, sdram and a led, it exhibits the same behaviour.

Yes I use PLL locked outputs as reset sources, but the reset code already compensates for possible locked signal toggling during resynchronization period after PLL reset is

deasserted. The design is fully constrained, there are no violations reported.