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Altera_Forum's avatar
Altera_Forum
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16 years ago

FPGA Impementation Digital Clock

Hi, I need to design digital clock allow global reset and allow user to adjust min and hour.I have done the min and second from 0 to 59 but i having a problem to design a counter 0 to 23. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

thk for your answer...

if using the structural how should i write it....