FPGA GPIO voltage falling

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I did some "debug", and found out, the problem was caused by my BIDIR ports of the SPI slave (my design enables QSPI). once i defined the port as input only, the voltage was O.k.

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Great! Its unlikely you damaged anything, since both drivers were "fighting" with about the same strength (no-one won).

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after some more debug, i realized, that for some strange reason, the FSM read flag was raised => the inputs were turned over to output (thus explaining why the voltage fell after the first byte...).

this is very wierd since i sent a"write" command, and according to my test block, the command was accepted correctly by the slave.

do you have any idea how could a signal go high even though on simulation it didn't?

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That sounds like a synchronization issue, eg., you're looking at signals from outside the FPGA that are not synchronous to your FSM clock. Check you have included synchronization logic where it is needed, and that you have correct timing constraints in your design.

This thread has a TimeQuest example for QSPI flash

http://www.alteraforum.com/forum/showthread.php?t=41009

Cheers,

Dave