Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

FPGA drive current effect on power draw in Cyclone IV

Howdy, With the Cyclone IV FPGA, we have run into some issues with noise on Vccio and Vccint pins while using the 24 mA default drive current. I found an application note (http://www.altera.co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

Either if you have explicitely impedance-controlled boards or not, changing the I/O current strength effectively modifies the driver impedance.

--- Quote End ---

Exactly. Higher drive strength = lower driver impedance = less time required to charge the capacitance of the trace plus the load capacitance = faster rise/fall times = length of traces which must be considered as transmission lines is reduced.

I'm aware that the discussion was about single-ended I/O standards, thank you. Perhaps I should have been more clear: A source termination resistor "might" be required at the driver to fully match the driver impedance to the transmission line impedance.