FPGA drive current effect on power draw in Cyclone IV

Either if you have explicitely impedance-controlled boards or not, changing the I/O current strength effectively modifies the driver impedance. It's a means to adjust the driver to match the trace impedance, which can be expected somewhere between e.g. 40 and 80 ohm for single ended traces with most multi layered PCB.

The discussion has been about single ended LVTTL/LVCMOS I/O standard, which usually can't be terminated at the load. In the speed range accessible by this I/O standard (e.g. 200 MHz), designed(calculated) rather than controlled(checked in production) impedances can be found with most PCB.