FPGA drive current effect on power draw in Cyclone IV

Kathryn,

Something you said in post# 7 caught my eye. You said that you were in fact having signal ringing problems, and not power supply noise problems? Can you elaborate a little? When you lower the drive strength of the I/O pins, you also lower the slew rate of the signal they are switching. Are you sure that the PCB traces are the correct impedance, and that transmission line effects aren't coming into play here? The rule of thumb that I use for determining if I need to treat a PCB trace as a transmission line is this: if the rise or fall time of the signal is less than twice the round-trip delay of the signal on the PCB trace (160ps per inch is good for back-of-the-envelope calculations), then you need to make sure that the trace impedance is controlled, and that the trace is also terminated properly. Ideally you would simulate the nets of concern in a high-speed simulator like HyperLynx, using your post-layout trace geometries and appropriate driver/receiver IBIS models before going to production. At any rate, if you can show on an oscilloscope that the signals ring too much at the receiver with the higher I/O drive-strength setting, but not with the lower drive-strength setting, then I would consider this problem solved.