FPGA-DAC PCB Design

To point out my position in this religion war: The concept of split planes is mainly an erroneous belief. Most designs are better with a continuous common plane respectively multiple stacked planes. You have to isolate sources of interfering currents, that can spread over the ground plane. In some cases, separated ground isles respectively local power plane areas can help, e.g. for SMPS functions. In- and outbound nodes are then bypassed against this local ground. Most digital and mixed signal devices are injecting common mode currents into the ground plane, they also cross the analog/digital boundary. With separate or split planes, these interfering currents can cause higher interference voltages on the board, you get possibly additional structural resonances and so on. The only convincing split plane designs I've seen are development kits, involving a single mixed signal device, e.g. an ADC. Unfortunately most real world designs can't follow this trivial topology.

The situation is different, if you leave the mixed signal region and go to low-level preamplifiers, output filters and similar functions for pure analog signals. They better reside on separate boards or possibly on an isolated region of a main board. But implementing well considered grounding schemes or even better, differential analog signaling, they can coexist with mixed signal design parts without problems.

Regarding the specific questions:

- A two layer PCB won't achieve a continuous ground plane, nor realize an ideal split plane concept. It's a compromise in everything. Practically, the ground will be split at the DAC position, so you can declare it as an implementation of whatever concept you prefer...

Even on a two layer board, you should be able to implement effective bypass caps.

- With Cyclone III, PLL issues have been considerably reduced by the internal VCCA regulators. Practically, local filtering of each PLL supply with multiple bypass caps and a ferrite bead or series resistor is the only option achievable with a two layer PCB. Strictly spoken, unused PLLs won't need this filtering.

- I expect, that SNR of your generator mainly depends on a good differential output amplifier design.