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Altera_Forum's avatar
Altera_Forum
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9 years ago

FPGA Counter Catch Eight game(error 10476, error 10558)

hi, im new to VHDL coding as im still learning the basics, i need to design a counter catch eight game and i have done the code but it shows and error and i am not able to solve it. it will be ver...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

So, 'Digit1_Output' is a 4-bit value. Which bit of that are you trying to connect your std_logic 'clock_output' to?

I suggest you change 

Digit1_Output: out unsigned(3 downto 0)

to 

Digit1_Output: out std_logic_vector(3 downto 0)

At the top level connect a new 4-bit std_logic_vector signal in place of 'clock_output' and then connect 'clock_output' to whichever bit of 'Digit1_Output' you need.

Cheers,

Alex