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You can attach any code to this post - I suggest the code for your 'Counter' module.
Cheers,
Alex
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---counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity Counter is
port(
CLK: in std_logic;
RST: in std_logic;
Digit1_Output: out unsigned(3 downto 0)
);
end Counter;
architecture Counter_arch of Counter is
signal Digit1: unsigned(3 downto 0);
begin
process(CLK,RST)
begin
if RST = '0' then
Digit1 <= (others=>'0');
elsif rising_edge(CLK)then
if Digit1 < 9 then
Digit1 <= Digit1 + 1;
else
Digit1 <= (others=>'0');
end if;
end if;
end process;
Digit1_Output <= Digit1;
end Counter_arch;
Honored Contributor
