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Altera_Forum's avatar
Altera_Forum
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9 years ago

FPGA Counter Catch Eight game(error 10476, error 10558)

hi, im new to VHDL coding as im still learning the basics, i need to design a counter catch eight game and i have done the code but it shows and error and i am not able to solve it. it will be ver...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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The 3rd port of your 'Counter' module is an 'unsigned' signal type and you're trying to connect 'clock_output', a 'std_logic' signal to it.

Cheers,

Alex

--- Quote End ---

hi mr alex,

if i send u my full code will be able to able to fix it for me because as i know i already the sign these signals in the counter. Are u able to help pls?? if can pls drop me ur email, i'll send u my full code in notepad :)