Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThe 3rd port of your 'Counter' module is an 'unsigned' signal type and you're trying to connect 'clock_output', a 'std_logic' signal to it.
Cheers, AlexThe 3rd port of your 'Counter' module is an 'unsigned' signal type and you're trying to connect 'clock_output', a 'std_logic' signal to it.
Cheers, Alex