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Altera_Forum
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17 years ago

FPGA Configuration with JTAG

Hey All, I have an interesting issue. I have a EP2C35F484 FPGA mounted on a FireflyII board (adds some memory, an oscillator, serial configuration chip and max232 converter). I am able to loa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

So it appears there is a problem loading the design onto the FPGA. When I tried to use signal tap on my design, Quartus responded saying "Error: Can't find the instance. Download a design with SRAM Object File containing this instance.".

I suppose this means the design is not being loaded. When I ran SignalTap on the NOIS design I was able to see all of the output signals without any issue.

So I guess this means the question has now moved to what is wrong with loading the design to the FPGA. I'll try to look for some differences between the NIOS design and my design but I definitely could use some guidance.

Thanks for the signal tap hint.

p.s. quartus version is: 7.2