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Honored Contributor
Honored ContributorFPGA Configuration with JTAG
Hey All, I have an interesting issue. I have a EP2C35F484 FPGA mounted on a FireflyII board (adds some memory, an oscillator, serial configuration chip and max232 converter). I am able to loa...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In my design I used the same output pins that were used in the working NIOS project. I just did a timing simulation and was able to see that my counter was working as expected. I've attached the schematic and the results below. Thanks http://i560.photobucket.com/albums/ss46/creeg2/schematic.jpg http://i560.photobucket.com/albums/ss46/creeg2/simresult.jpg --- Quote End --- Hi, on the schematic I don't see any reason, why it should not work. Can you post the whole project? What kind of Quartus version did you use ? If you have a version which includes signaltap, try to tap one of your internal signals in order to make sure that the design is loaded. Kind regards GPK
