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Honored Contributor

17 years ago

FPGA Configuration with JTAG

Hey All, I have an interesting issue. I have a EP2C35F484 FPGA mounted on a FireflyII board (adds some memory, an oscillator, serial configuration chip and max232 converter). I am able to loa...

Altera_Forum

Honored Contributor

17 years ago

In my design I used the same output pins that were used in the working NIOS project. I just did a timing simulation and was able to see that my counter was working as expected. I've attached the schematic and the results below.

Thanks

http://i560.photobucket.com/albums/ss46/creeg2/schematic.jpg

http://i560.photobucket.com/albums/ss46/creeg2/simresult.jpg

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FPGA Configuration with JTAG

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