FPGA Configuration with JTAG

I'm using one of the example applications that come with the NIOS design suite: http://www.altera.com/support/examples/nios2/exm-hello_free.html. The design was already inserted into a schematic. All I had to do was assign the LED output pins. This simple counter example works and I am able to view the output using a simple digital analyzer scope. In my vhdl, I am simply assigning the clock input pin to one of the same output pins that I used in the NIOS counter. There is no difference between the way I tested the two designs.