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Altera_Forum's avatar
Altera_Forum
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17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Johnson,

Do you mean PFL loads data successfully with one data and fails another?

Would you upload PFL design that you put counter to delay starting PFL? I will check it anyway.

Thanks