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Altera_Forum
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17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Take a look at this document:

http://www.altera.com/literature/hb/agx/agx_52011.pdf

Any chance the pull-up on conf_done or nStatus is missing?

Posting the .cof file and the PFL megawizard generated .v or .vhd file might provide some clues. What is MSEL(3:0) set too? Is the .sof file you are using have compression enabled(see figure 11.1 of above document)?

If you are using compression, read pages 11-5 and 11-6.