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Honored Contributor
Honored ContributorFPGA configuration time and PCIe secification
Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme? I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interf...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The 9ms POR delay is what the "reset supervisor" delay inside the FPGA implements, and worst-case it is 9ms. Sorry, I missed including that delay in the posting earlier in the day. So your power-on time calculation is tRAMP + tPOR + tCFG, where tCFG is the bit-stream configuration time. --- Quote End --- What is "reset supervisor" delay inside the FPGA? I don't see any straight-forward statment in Handbook, that tells to add tRAMP + tPOR, that is 3ms + 9ms.
