FPGA configuration time and PCIe secification

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I found Your paper ( cpci_power_on_timing.pdf ), that calculates total configuration time for EP4CGX15.

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Here's the more complete version of it;

http://www.ovro.caltech.edu/~dwh/wbsddc/ts4_power.pdf

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Here is a quote from it:

the configuration time for a cyclone iv gx ep4cgx15 configured via fast passive

parallel (fpp) mode using a 66mhz clock is; 3ms power-supply ramp + 9ms power-onreset

delay + 3,805,568-bits/66mhz = 70ms.

Of course FPP is not applicable to EP4CGX15, but the calculation is also misleading...

Please explain why did You interpret Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2) in such a way: "3ms power-supply ramp + 9ms power-onreset delay"?

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Hmm, let me try to remember ... :)

The first error I notice is that I said FPP, but the calculation is for PS mode (since there is no divide-by-8).

The 3ms power-on-ramp comes from the hardware design, eg., see p18 of the PDF I just linked to, so that is design-specific, but it is what you must implement when you select MSEL for Fast POR, i.e., tRAMP < 3ms.

The 9ms POR delay is what the "reset supervisor" delay inside the FPGA implements, and worst-case it is 9ms. Sorry, I missed including that delay in the posting earlier in the day.

So your power-on time calculation is tRAMP + tPOR + tCFG, where tCFG is the bit-stream configuration time.

In reality, if you are conservative and target tCFG < 50ms, all the other small time values do not matter. If for example you use FPP mode, then the configuration time is a small fraction of the 100ms requirement, so its no problem ... until of course you use a large Stratix V device ... but then you can use CvP.

Cheers,

Dave