FPGA configuration time and PCIe secification

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The timing parameters are in the response above; you have the power-on time of tRAMP < 3ms, after which point the POR time completes, the device deasserts nSTATUS and starts the configuration process. Look at the AS mode timing diagram for the "extra" delays - but they're microseconds, so can be ignored if you set your 100ms limit a little lower, eg., 95ms.

Cheers,

Dave

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I found Your paper ( cpci_power_on_timing.pdf ), that calculates total configuration time for EP4CGX15.

Here is a quote frome it:

the configuration time for a cyclone iv gx ep4cgx15 configured via fast passive

parallel (fpp) mode using a 66mhz clock is; 3ms power-supply ramp + 9ms power-onreset

delay + 3,805,568-bits/66mhz = 70ms.

Of course FPP is not applicable to EP4CGX15, but the calculation is also misleading...

Please explain why did You interpret Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2) in such a way: "3ms power-supply ramp + 9ms power-onreset delay"?

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