--- Quote Start ---
Now getting back to the very beginning to what I was asking for:
What timings ( POR-related, etc. ) I have to add to calculate that extra time?
--- Quote End ---
The timing parameters are in the response above; you have the power-on time of tRAMP < 3ms, after which point the POR time completes, the device deasserts nSTATUS and starts the configuration process. Look at the AS mode timing diagram for the "extra" delays - but they're microseconds, so can be ignored if you set your 100ms limit a little lower, eg., 95ms.
If you have an FPGA development kit, eg., a DE0-nano, then go and measure the signals on that board too. That will give you a good idea of how well the handbook numbers reflect reality.
Cheers,
Dave
Honored Contributor
