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On the HP system I have and the Altera Stratix -V development card with SignalTrap configured for a Power-up Trigger, I don't seem to capture the slot PERST_N signal
rising edge. However the card still comes up active and is enumerated. I am able to trigger on the PERST_N signal rising edge when I perform a restart operation and the FPGA remains powered up and running.
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I'm not sure how reliable SignalTap II is when using the power-on trigger. Personally, I would probe the CONF_DONE signal and the PCIe RST# signal and look at their relative timing.
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There is a possibility that if the power on PERST_N is long enough, say 100 ms, then if the FPGA is configuring during the 100mS , there is an additional 100 ms
from the end of the fundamental reset , PERST_N, until the FPGA needs to be ready to receive configuration requests. ( per Add-in Card System Architecture Checklist )
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Yeah, there's all sorts of ambiguous statements throughout the PCIe documentation. There's often the statement that the ability for the system to meet the power-on reset timing requirement is the responsibility of the system integrator. In my case, I define the host CPUs and the PCIe boards, so I can adjust the timing to meet my custom requirements, however, for commercial products, its important to be conservative. Since FPP can easily meet the timing requirement, that is the best way to go. In your case, you're subject to whatever the Stratix V kit implementation is.
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Not sure how to include an image here ...
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I think the advanced viewer has a button you can use to add an image, or you can just upload a file.
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I could compute the configuration time for the Stratix-V and figure out the endpoint card power rail stable time that will then start the configuration load via the MAX chip.
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Its a good exercise in understanding how the board was designed. Go and look at the MSEL settings, and the schematic.
Cheers,
Dave
Honored Contributor
