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EP4CGX15 and EP4CGX22 ( which I need ) do not support FPP.
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They do however support PS mode, so you can use that mode to ensure the timing is met.
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EPCS4 cost can fall below 1 USD if M25P40 is used instead. It has the same mfg ID.
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Yeah, the QSPI flash can also be used, it responds to the same command codes.
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The only problem is ( I overlooked it ) is that typical DCLK for AS mode is 33 MHz instead of 40 MHz as I expected.
Maybe its because internal oscillator is used to create the DCLK?
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No idea, but of all the devices I have probed with a scope, the AS mode configuration DCLK signal is always close to 33MHz.
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Did You ever test CLKUSR mode?
If Yes, then what do You think about setting DCLK=40MHz in CLKUSR mode?
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I have not used CLKUSR mode. I typically have a MAX II device on the board anyway, so implementing PS or FPP mode is not much effort.
p169, Table 8-2,
- EP4CGX15 => 3,805,568/40MHz = 95ms
- EP4CGX22 => 7,600,040/40MHz = 190ms X FAIL
The EP4CGX15 is close, but by the time you add in the POR delay, and any power supply delays, eg. due to hot-swap controller or power manager IC, then you might be out of time.
Compression might help you get under the limit. If your PCIe end-point logic will never change, or is completely under your control, then you could use this scheme. If however this is supposed to be a product that an end-user can configure the PCIe FPGA with arbitrary logic, then you should add a disclaimer regarding the ability of the design to meet the PCIe power-on requirement.
Cheers,
Dave
Honored Contributor
