FPGA can't properly work at my input CLK.

In my design,I found the clock can not properly work.

The input clock is 66Mhz, if this signal directly is connected to the output pin, the output will get a signal of 66MHz. That's ok.

but!!!!!!

If this signal go through a PLL ( divided_by 1 and multiplied_by 1) ,and then is connected to the output pin,the output will get a signal of 132Mhz. That's wrong!!!!!!!

https://www.alteraforum.com/forum/attachment.php?attachmentid=9116

The logic of my design should work at 66Mhz, But it can not work at 66Mhz now.

please help me...........

quartus version: 13.0

device: EP3C55F484I7

PIN_T1: 66MHz input