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ABelo9
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7 years ago

For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

The VCCIO is 3.3V. Thank you!
ABelo9's avatar
ABelo9
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7 years ago

Thank you for your help, Anand!

Best regards,

Andrey