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Altera_Forum's avatar
Altera_Forum
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10 years ago

Fmax of design

Hi, I designed a processor using VHDL on Quartus II, but I didnt know how to determine its fmax. Where in quartus can report this? Or I should be use ModelSim to check it? Thank you
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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I dont understand what is slow 1200mV 85C model? What is 85C? Celsius?

I set up clock, set input delay, set output delay with 100ns, slow model, fast model are not red. So, fmax in those reports is Fmax of design? And onnly Unconstrained paths is red. What should I do with this red? Thank you.

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That means the timing analysis assumes that the chip is running with a core voltage of 1200mv at 85 degrees celcius. This is what will usually cause the biggest delays in the chip.

Set input and output delay are meant to compensate for track lengths on your PCB so that signals can be skewed relative to an input clock. They dont affect the FMax.

Timequest will not tell you operations per second. You must know how many clocks there are per operation. So for a given FMax, you can calculate number of ops/s