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Altera_Forum
Honored Contributor
Honored ContributorFmax Improvment
I'm trying to improve Fmax in our design. See the archived quartus II proejct file in the attachment. The source files are also attached. In my currrent design, after compilation, Fmax can reach ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This still builds a priority encoder, as in VHDL the last assignment always takes priority. And if you're only getting an FMax of 60MHz, there are still probably some long logic paths. You should use Timequest to find the worst paths, and then try and reduce the logic. --- Quote End --- Hello Tricky, Thanks for your help. Is it possible you can show me some code to explain your idea?
