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Altera_Forum
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11 years ago

Fmax Improvment

I'm trying to improve Fmax in our design. See the archived quartus II proejct file in the attachment. The source files are also attached. In my currrent design, after compilation, Fmax can reach ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This still builds a priority encoder, as in VHDL the last assignment always takes priority.

And if you're only getting an FMax of 60MHz, there are still probably some long logic paths. You should use Timequest to find the worst paths, and then try and reduce the logic.