Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Fmax Improvment

I'm trying to improve Fmax in our design. See the archived quartus II proejct file in the attachment. The source files are also attached. In my currrent design, after compilation, Fmax can reach ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You could probably setup all of the compare values on the previous clock cycle, and then setup some signal so that a case statement is viable instead of the if/elseif chain. if/elsif will create a priority mux if the cases are not mutually exclusive, which is slower than a normal mux (that you get from a case statement).