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Altera_Forum
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11 years ago

Fmax Improvment

I'm trying to improve Fmax in our design. See the archived quartus II proejct file in the attachment. The source files are also attached. In my currrent design, after compilation, Fmax can reach ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yeah, just do shift_right in one clock cycle, add in another and lesser in another.

Pipeline is just a FFs that are unused in combinatiorial-logic-only LEs.

If you are run out of resource you can't scale up frequency..