Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Fmax Improvment

I'm trying to improve Fmax in our design. See the archived quartus II proejct file in the attachment. The source files are also attached. In my currrent design, after compilation, Fmax can reach ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You can find a lot of examples of pipelines in books and on web. Have you found where to insert pipeline in VHDL?