Occasional Contributor
Super ContributorHi Alex.
The JTAG line to FPGA might not have signal integrity issue, that's why you can successfully program .sof file.
However, the line between JTAG to flash might have signal integrity issue. Hence that is why you need to reduce the TCK frequency.
Please check the routing from JTAG header to flash. Also, check your board layout to make sure there is no SI issue.
Make sure you refer to EPCQ-A configuration datasheet.
Regards,
Aiman
Occasional ContributorHello
JTAG connector is not connected directly to the flash, it is connected to FPGA only and serial flash loader is used to program the flash.
The connection is done according to a following schematics:
As I wrote also FPGA configuration from the flash running in 40Mhz is done correctly.
All nets between JTAG - FPGA and FPGA - flash are handled very carefully and matched in length with reference to TCK/DCLK.
So personally, I suspect that the problem is with SFL IP (it can't work in 24Mhz or not initialized and etc...)??
Also, why USB blaster II running on 16Mhz is much slower than Terasic running on 6Mhz?
Thank you
Alex
