Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Since 0.16 * 2.14 = 2.30 (32 bits), would restricting output to 16-bits give 2.14? [x.y -> x=decimal bits and y=fractional bits] --- Quote End --- altmult_complex knows nothing about fixed point, as you may have noticed. Restricting it's output it will give you the 16 less significant bits, which is not what you want. Instead, you can either a) use altmult_complex with a 32 bit output and then just select the 16 MSBs. b) use VHDL's complex package c) do it by hand in VHDL Any way is a good way.