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Altera_Forum's avatar
Altera_Forum
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10 years ago

Fitter error: can't place fractional PLL in Cyclone V ST.

Hi,

I have a design that uses the Hard Memory interface for the HPS and for the FPGA DDR memory. If I add a regular PLL to this design from an I/O pin in bank 3A (bank 3B and 4A are the DDR banks for the FPGA DDR memory), then it claims it can't fit a Fractional PLL because of pin constraints. Why does using the DDR memory stop me using any of the other clock inputs to run a PLL? Makes it fairly pointless having a device with 15 PLLs.

And why does it try and place a fractional PLL when I don't need the fractional bit?

Any help appreciated.

Simon

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You will have to use the same I/O-Standard for the Clock, driving the PLL as for the PINs which it is driving. Therefore you may also want the PLL of the dedicated Bank to be used to solve the problem. Global Clock-Nets are rare, so do not overuse them for simple things. Maybe if you want to, you may want to have a look at the Clock-Buffer-IP, which I don't recommend. Maybe also a free-run of the fitter (without PIN-Assignments for the Clock-Input) will help to decide the right one.

    If you have further concrete questions do not hesitate to ask.