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Altera_Forum
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12 years ago

First time CPLD use questions - internal pull up resistor and clocking with Max 7000S

I've designed a video game controller using Altera Max 7000s and Quartus 2 using the BDF process. 1-Was I suppose to add a clock? I only have inputs and outputs and logic gates needed in the ...
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Altera_Forum
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12 years ago

If you only use combinatorial logic, a clock is not strictly required.

However, in a typical design you have a least one register or a few synchronous functions, so you usually do need a clock.

Some CPLD and FPGA have internal clocks available, but they are far from being at precise frequency, since they are generated without a crystal. So, they can be used for very basic clocking, but not for something like driving serial ports or similar functions requiring a stable frequency reference.

No matter setting inputs connecting them to VCC or GND: this is what we common do for test purposes. The CPLD internal pull up resistors are not a problem since they usually have a high value, in the tens-of-kohms range. You only must pay attention to not exceed the I/O input voltage range.