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alperenpalp's avatar
alperenpalp
Icon for New Contributor rankNew Contributor
5 years ago
Solved

FIR II core IP outputs incorrect data.

Hello, It's my first time using intel's FIR filter IP and I'm having difficulties getting it working. I basically want to low-pass filter the data coming from the ADC (LTC2387) using FIR II IP. T...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    Would you mind to help opening a new thread on this. Thank you very much.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. As I understand it, you are observing this in signaltap. To help isolating any functional issue, it is recommended for you to create simple test design and run through Modelsim simulation to check on the behavior. Generally the Modelsim simulation behavior is similar to the hardware behavior for this IP. This would help to isolate any functional issue prior to hardware debugging. Please feel free to keep me posted on the simulation result.


Regarding the ast_sink_error, this is to indicate AVST violation to the IP. In normal cases, you can drive the ports with 2'b00.


Regarding the SOP/EOP, yes, you are right. For single channel, you do not need these ports. By default, when you select single channel, there will be no SOP/EOP ports.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin



  • alperenpalp's avatar
    alperenpalp
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank you for your kind response,

    OK I am going to start with a testbench, but I want to quickly confirm one thing. Is Singed binary same as bit magnitude where the first represents the sign and the rest is the number. I am talking about Input and output type in Input/Output Options settings.

    I wrote a simple test bench and tested the FIR filter (attached). I share the results with a screenshot. As you see the input is fixed at some value, the clock to the filter is 60 MHz and every fourth cycle of the I asserted the sink_valid signal for one cycle and I see don't see any output. No action from the filter.

    See the attached files for the test bench it's named FIR_tb.vhd. I know there is another tb file generated by quartus, but failed to get it working. I simply instantianted pre_process_FIR_20MSPS_0002 IP and tried to get it working.

    FIR_tb.vhd

    Thanks in advance.