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Altera_Forum's avatar
Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
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14 years ago

k,

any news regarding your issue? Have you been able to solve it?

I took another quick look on the files you'd attached, and I might have found out what could be causing your issue. How are you CLOCKING your design? What frequency are you providing AD7401 with, and what frequency do you clock your design with? If you're using different clock domains, you might want to try clocking the whole design with the same frequency.

Let us know how you're doing!