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Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
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14 years ago

1、I don't know why it can't work.Is it right to create symbols of VHDL and verilog program and then put them together in a block diagram to compile?(Set the block diagram as the top-level entity)

The program of vhdl I used can't work in the block diagram.I set the word_clk as output pin and observe it by scope and can't get any square wave.

=> The problem above has been solved.

But it works not correctly.Because the DATA[15..0] I get was not stable and fluctuates about 1000,which it's terrible for the measure of a fixed voltage.

2、The word_clk signal is get by dividing the signal of mclk.

decimation rate=Divider ratio=f(mclk)/f(word_clk)

The frequency is got as follows:

sysclk (50MHZ Crystal ) -> MCLK(6.25MHZ drive the AD7401 ) ->word_clk (decimation rate=256,24.41KHZ to enable the Differentiators)