Filter & decimation implementation on AD7401

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I used the code you write to debug to the actual circuit not simulation, and found it cannot produce WORD_CLK clock signal, so I have written in verilog a divider circuit, to produce mclk and word_clk signal.

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And why don't you get a valid word_clk signal? Apparently it worked in the original design.

Whatever the problem is, there have been good reasons to use word_clk as a clock enable instead of a divided (or so called "ripple") clock for the slow CIC frequency. A ripple clock brings up timing violation for the domain crossing signals, it's just a bad design method.