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Altera_Forum
Honored Contributor
Honored ContributorFifo
HI, I am trying to impliment a megawizard fifo in my design.
Can anyone advise me on the inputs or have an example design? I dont understand what each input does and what I should be putting into them. The manual isn't very helpful. Mainly wrreq and rdreq inputd. Thank you in advance for your help.3 Replies
Altera_ForumFixed - had a typo on the input.
- Altera_Forum
HI, thanks for your help.
Is there a not simpler example with .bdf with connections shown? Aslo I get this error when I try to put the output from the my fifo into my nios II core Error: WYSIWYG primitive "fifo_vhdl:inst19|scfifo:scfifo_component|scfifo_ov71:auto_generated|a_dpfifo_v581:dpfifo|dpram_n261:FIFOram|altsyncram_g2m1:altsyncram1|ram_block2a13" has mismatched parameters for port Port A, Data In Any ideas? Thank you - Altera_Forum
Please take a look at following AN and example design.
http://www.altera.com/literature/an/an473.pdf http://www.altera.com/literature/an/an473_design_example.zip
