Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

FIFO output BigEndian or LittleEndian!

hi,when using FIFO of LPM,output width is made different from input width,if I make input[63:0] and output[7:0],the waveform shows that the output starts from the LSB of the input ,ie,[7:0]、...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The FIFO is little endian so if you want the output to be big endian then like tentner said reverse the byte lanes of the input before the data enters the FIFO. This is just wires and will not affect the timing or latency at all.

So if your 64 bit input to the FIFO was called "data" and you want to reverse the data just do something like this (in verilog) and pass "reversed_data" to the input of the FIFO instead:

assign reversed_data = {data[7:0], data[15:8], ...... ,data[55:48], data[63:56]};